Senior Analog Mixed Signal Design Engineer - Acacia
Lieu :San Jose, California, US
Centre d'intérêtIngénieur - matériel
Type de posteExpérimenté
Intérêt pour la technologieCloud et data center
ID de poste1341837
Acacia designs, develops, manufactures and sells intelligent transceivers using sophisticated signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.
The Sr Analog/Mixed-signal IC Design Engineer will be a key member in a small, dynamic IC Design team that develops high speed analog designs for optical communications products. He/she will architect, design, layout, measure and productize ultra-deep sub-micron based products.
- Collaborate with the mixed-signal team and system teams to define and specify the requirements
- Responsible for the analog circuit, layout design, and testing of analog/mixed signal circuitry for high speed (>10GS/s) and high accuracy analog designs
- Review complex IC designs and make any necessary recommendations for improvements
- Apply and drive solid design methodology from conception to production
- Influence packaging and hardware design team to ensure signal and power integrity specifications are met
- Lead a large block on a complex chip and mentor some engineers on an as needed basis
- Perform other duties as assigned
- Typically requires a BSEE degree with 8+ years of relevant experience or an MS degree with 5+ years of experience or a PhD with 3+
- Design, simulation and measurement of high speed ICs using CMOS and CML circuits in at least 3 areas below:
o Serializers and deserializers
o Digital-Analog Convertors
o Analog-Digital Convertors
o Voltage Regulators
o High Performance Output Drivers
o High Performance Phase Locked Loops
o Efficient clock
o Opamps and Programmable Gain Amplifiers
o Equalization techniques
- Direct experience with electrical transceiver applications including backplane and cable communications.
- Experience with FinFET technology or 16nm or below technology node
- High-frequency layout experience a plus:
- Passive component design: inductors, transformers, transmission-lines, etc… Floorplanning (power/ground, digital/analog signal routing, etc…) Custom transistor layout.
- Design for manufacturability:
Characterization over PVT (monte-carlo analysis)
Electromigration analysis (using Totem, or equivalent)
Power and IR drop analysis
- Laboratory Validation:
Solid ESD laboratory practices and methodology Construction of test setup to test specific circuitry Experience in the use of high frequency test equipment (BERT, jitter analyzers, VNA, etc.)
- Software Experience:
Cadence (virtuoso) Spectre/APS Layout validation tools (Virtuoso or Calibre) Post-layout Extraction (Virtuoso or Calibre) EMX Mixed-signal simulations in AMS
- Collaborative team player who can work independently.
- Possess a track record of innovation. Publications are a plus.