ASIC Design Verification Engineer II

  • Lieu :
    San Jose, California, US
  • Centre d'intérêt
    Ingénieur - matériel
  • Type de poste
  • Intérêt pour la technologie
  • ID de poste

Will participate in the ASIC design verification for Cisco Enterprise high-end switching products.


Responsibilities include the development of simulation models, test plan, direct and random tests, code or functional coverage,

multi-chip/system simulation, and performance analysis. Requires good communication skills to interface with the hardware, software

designers and vendors. Applicant must be capable of working independently. Must be a good team player.



Typically requires MSEE/CS combined with 0-2 years of related experience, or BSEE/CS combined with 2-4 years of related experience. 


Skills required:

Must be proficient in SystemVerilog/UVM. Knowledge of Linux is essential. C/C++ and Python/Perl are preferred. Must be familiar with ASIC design and verification processes and tools. Must have strong

debugging skills. Knowledge of Networking is preferred. Experience with Formal verification is a plus. 


Understands product level architecture. Ability to multitask. 

 Ability to solve problems of moderate scope involving multiple modules. Works under general supervision.  Follows established procedures. Work is reviewed for soundness of technical judgment and overall adequacy and accuracy. Excellent written and verbal communications, team and people skills. Shares information and communicates clearly to team members. Encourages and accepts personal feedback. Promotes cooperation between team members. 

Uses acquired professional knowledge to make decisions, works on problems of moderate scope. Exercises judgement within defined standards and consults with management. Technical Knowledge.  

Teamwork.  Solve Problems & Make Decisions.