Technical Lead Asic Package Design Engineer
Location:San Jose, California, US
Area of InterestEngineer - Hardware
Design, Route, model and validate silicon package substrate designs critical to high speed networking product requirements. It is critical to understand manufacturing design rules, Signal Integrity and Power Integrity requirements to minimize package iterations and create working designs.
Setup the design, create routing standards and implement package route to meet the rules required for very high speed serdes and large pin count devices.
The role will require interaction with an asic team and foundry suppliers. Electrical modeling and iteration with pcb, connector, and asic team will be required. Focus will be primarily on flip chip packages and heterogeneous integration chip package design.
Capability of understanding and driving to milestones to make development successful.
A complete knowledge of packaging materials and material properties is needed. The knowledge of 2.1D, 2.5D and interposer integration is a plus.
A working knowledge of Cadence Allegro Packaging Design (APD) is a must. Experience with v17.2 of APD and Cadence System in Package (SiP) is a plus. A familiarity with Ansys HFSS and SiWave is a plus. Additional knowledge of Icepak, XtractIM and PowerSI will be beneficial.
BS in Electrical Engineering or related field, or equivalent experience.
7 or more years in the industry with packaging development.
Experience with several high pin count, high power and high speed packages.
Strong communication, problem solving, interpersonal and presentation/documentation skills.