Sr. IC Layout Engineer
Area of InterestEngineer - Hardware
Technology InterestCloud and Data Center
We are looking for a highly motivated and knowledgeable layout engineer with a deep understanding of CAD tool infrastructure to work on photonic ICs. The PIC Layout Design Engineer will be a key member of a small, dynamic Photonic IC design team that develops silicon photonic IC’s for Acacia’s (now part of Cisco) optical transponders. This position presents a unique opportunity to work closely with our PIC, mmW IC, ASIC, and packaging teams.
In this role, he or she will perform the following key essential functions:
- Layout basic optical components together with PIC design engineers.
- Design power, ground, low and high speed signal interfaces between optical components and DRVs and TIAs together with mmW IC team and packaging team.
- Manage internal PDKs.
- Own the mask assembly process of our PIC tapeouts, including managing DRC deck and flow, fill, reviewing of signal routing, etc.
- Own specification documentations for PIC, for interactions with packaging, module hardware and software team. This includes pad frame / signal definitions, mechanical drawings, etc.
Desired qualifications and experiences:
- Bachelor’s degree or equivalent in EE or training in layout design.
- Industry experience of a minimum of 5 years in layout design.
- Extensive knowledge of Mentor, Synopsys and Cadence toolsets
- Extensive layout experience in analog and RF ICs.
- Deep understanding of low parasitic, high frequency design techniques.
- Strong knowledge of IR drop, RC delay and Electromigration.
- Experience with RF modeling and/or signal integrity is a big plus
- Ability to script and automate layout tools and flow a huge plus
- Knowledge or experience with Cadence Clarity a huge plus
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