Sr. Asic Design Engineer
Location:San Jose, California, US
Area of InterestEngineer - Hardware
- Participate in the development of high-performance ASICs from specification to tape-out, including RTL, synthesis and physical design/timing closure
- RTL design
- Participate in the Implementation of new designs using Verilog/SystemVerilog
- Maintain and improve existing designs from timing, power and area
- Actively work with the verification team to deliver ASICs with high quality
- Triage and troubleshoot failures down to the root cause both during pre-silicon verification and post silicon validation
- Perform diagnostics and tests for ASICs in the lab
- Physical Design
- Work with ASIC vendors and internal physical design teams to resolve implementation and timing issues at block/top-level
- Participate in developing flow/tool methodologies
- IOs and analog macros (serdes, pll & etc) selection and placements
- Maintain power/area spreadsheets
- Entry/exit criteria and checklists for intermediate and final milestones.
Education and Experience Required :
- Bachelor’s or Master’s degree in Electrical Engineering.
- 15+ years of ASIC design experience.
- Hands on experience in RTL Design and/or physical design.
- Strong experience with Design tools/methodology, PD tools, Synthesis, Timing and Power Analysis.
Preferred Qualifications :
- Experience and familiarity with high speed interfaces like PCIE, Ethernet, DDR, Peripherals (I2C, Uart, eSPI & etc).
- Strong understanding of ARM CPU and ARM IPs implementations, Interfaces such as AXI, PCIE, Ethernet and DDR.
- Familiarity with high performance and low power design techniques.
- Detail understanding of clock gating techniques and familiarity with power gating (voltage islands) is strongly desired.
- Prior experience with low power analysis / optimization tools like PowerArtist / Innergy is a plus.
Knowledge and Skills :
- Excellent Verilog, System Verilog coding and debugging skills.
- Scripting experience (Python, Perl, TCL, shell programming
- Proficient in synthesis constraints and timing closure with tools like Primetime
- Experience with power analysis with tools like PTPX
- Ability to debug system-wide issues.
- Good written and verbal communication skills.
- Collaborative and team-focused with the drive to learn and grow.