Sr. Analog/Mixed-signal IC Design Engineer - remote
Location:San Jose, California, US
Area of InterestEngineer - Hardware
Technology InterestCloud and Data Center
The Analog/Mixed-signal IC Design Engineer will be a key member in a small, dynamic IC Design team that develops high speed mixed-signal designs for coherent optical communications products. This team has track record of developing ultra-high speed (>100 Gsps) data converters in latest FinFET nodes. This engineer will architect, design, layout, test and productize ultra-deep sub-micron based products.
- Responsible for analog circuit, layout design and testing of analog/mixed signal circuitry for high speed (>25GS/s) and high accuracy Analog designs
- Work with the mixed-signal and system teams to specify the requirements
- Candidate (depending on experience) might be required to lead a large block on a complex chip and mentor some engineers.
- Peer review of complex IC designs
- Solid design methodology from conception to production
- Work with packaging and hardware design team to ensure signal and power integrity specifications are met
Minimum Qualifications, Experience, Skills, Education and Certifications:
- Typically requires a BSEE degree and 9 years of experience or an MS degree and 6 years of experience or a PhD and 3 years of experience. Outstanding fresh PhD graduates would be considered as well.
- Design, simulation and measurement of high-speed ICs in at least 3 areas below:
- High speed Time-interleaved ADC
- Tuned high frequency circuits
- Resonant Clock Circuits, Clock distribution and Low power Clocking Techniques
- Digital fractional-N phase-locked loop (PLL)
- High speed Time-interleaved DAC and Output Drivers
- Digital calibration of analog circuit imperfections
- Voltage Regulators
- Opamps and Programmable Gain Amplifiers
- Equalization techniques
Highly Desired Skills:
- Experience with FinFET technology.
a) Passive component design: inductors, transformers, transmission-lines
b) High-frequency layout experience a plus.
c) Floorplanning (power/ground, digital/analog signal routing etc.)
d) Custom transistor layout.
e) Characterization over PVT (monte-carlo analysis)
f) Electromigration analysis (using Totem, Voltus-Fi or equivalent)
g) Power and IR drop analysis
- Laboratory Validation:
a) Solid ESD laboratory practices and methodology
b) Construction of test setup to test specific circuitry
- Software Experience:
a) Cadence (virtuoso)
c) Layout validation tools (Virtuoso or Calibre)
d) Post-layout Extraction (Virtuoso or Calibre)
f) Mixed-signal simulations in AMS
- Collaborative team player who can work independently.
- Possessing a track record of innovation. Publications are a plus.
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The health and safety of Cisco's employees, customers, and partners is a top priority. Our goal is to protect and mitigate the spread of COVID-19 infection for strong business resiliency during the pandemic. Therefore, Cisco may require new hires to be fully vaccinated against COVID-19 if the role requires business-related travel, meeting with customers/partners (including visiting third-party sites on behalf of Cisco), attending trade events, and Cisco office entry, unless otherwise prohibited by applicable law, and in countries where COVID-19 vaccination is legally required. The company will consider legally required accommodations/exceptions for medical, religious, and other reasons as per the requirements of the role and in accordance with applicable law. Additional information will be provided to candidates about the requirements and accommodation process at the offer time based on region.