Sr. ASIC design verification engineer.
Location:Taipei, T'ai-Pei Shih, Taiwan
Area of InterestEngineer - Hardware
• 5 - 10 years in ASIC design verification.
• Hands-on experience on Verilog HDL verification
• Experience of high performance ASIC design flow from specification to system bringing up
• Knowledge of System Verilog and UVM verification methodology
• Highly motivated, positive, detail oriented and responsible
• Good team player and good communication skills