Sr. ASIC Design Verification Engineer

  • Location:
    Taipei, T'ai-Pei Shih, Taiwan
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    Networking
  • Job Id
    1301836

Senior ASIC verification.

Experience Required

5 - 10 years in ASIC design verification.

Hands-on experience on Verilog HDL verification

Experience of high performance ASIC design flow from specification to system bringing up

Knowledge of System Verilog and UVM verification methodology

Highly motivated, positive, detail oriented and responsible

Good team player and good communication skills

MSEE/MSCS


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