Signal and Power Integrity Lead Engineer
Location:San Jose, California, US
Area of InterestEngineer - Hardware
Technology InterestCloud and Data Center, Networking
What You Will Do
Cisco Silicon One ASIC team is looking for a professional in Signal Integrity and Power Integrity of electrical interfaces and IP to help us development our next generation silicon and platforms. You will have package and board integration responsibilities with hands-on experience on high speed serdes and modern high-speed interfaces. In addition, you will be involved in substrate development and all signal and power integrity requirements to make a new silicon product successful. You will extend a track record of leading similar products to manufacturing.
Who You Will Work With
Cisco Silicon One is a business organization building and selling ASICs inside and outside of Cisco. We have a long track record of building Silicon ASICS for Cisco’s internal platforms. We are a focused ASIC team with specialists in all aspects of Silicon Design and system integration. We are focused on all the latest signaling and data transfer technology including optical and advanced packaging.
Who You Will Be
You will be an signal and power integrity engineer working on the latest technologies and developing ASIC substrates that push the boundary on power and signal integrity. The Power requirements and signaling speeds are only required by a small number of Silicon teams. Modern ASICs will only work if the power and signaling solutions are identified and implemented. You will be working on the world’s most complex networks powered by silicon that carries over 90% of IP traffic.
Looking for signal integrity specialist to focus on package analysis and system ASIC integration. The responsibilities will range from IP analysis and planning with overall analysis of signal integrity to full electrical planning and specification of electrical interfaces. An understanding of Serdes, signal integrity and power integrity is critical. The role will drive Signal Integrity and Power Integrity requirements for the ASIC integration. Work will be with PCB and ASIC teams on power, Serdes and signal integrity. Final analysis and validation of IP and high performance compute subsystems in a lab environment will be required.
- Package planning and integration for asic-package-pcb subsystem.
- Package specification and analysis for High Speed Serdes function.
- High Speed Serdes power on, validation and characterization
- Advanced package analysis for HBM and modern packaging technologies.
- Low level device programming/scripting in a lab environment.
- Specification and analysis of power and high speed signaling (ASIC-Package-Board-Cabling) for advanced networking boards.
- Working with diverse teams on high power and thermal management of systems.
- Capability of understanding and working towards breakthroughs to make development successful.
- Knowledge of package and/or PCB materials and material properties. Knowledge of 2.1D, 2.5D and interposer integration is a plus.
- Circuit board development for ASIC evaluation and validation.
- Hands-On lab experience with electrical bringup and characterization.
- Basic scripting (Perl, Python, excel, etc) for data analysis and lab characterization.
- Basic Cadence Allegro and/or a working knowledge of Cadence APD/SIP.
- SI/PI Tools including Ansys HFSS, SiWave, Cadence Clarity/Sigrity
- Lab hardware including oscilloscopes, VNA, PSU and electrical characterization.
- Knowledge of Linux and running related SI-PI tools in a Linux environment.
Degree in Electrical Engineering or related field, or equivalent experience. 2 or more years in the industry with experience on high performance circuit boards. Experience with large, high power and high speed components. Strong communication, problem solving, interpersonal and presentation/documentation skills.
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