Signal Integrity Technical Leader

  • Location:
    Shanghai, China
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
  • Job Id


What You'll Do:
- Working directly with ASIC and System design teams to evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability
- Drive next generation Serdes IP characterization
- Driving next generation ASIC/system feasibility studies
- Design and analysis of multi-gigabit serial links and their compliance to standards 
- Electromagnetic modeling of complex 3-dimensional structures
- Perform pre- and post-route signal integrity analysis of both PCB and ASIC package designs
- Generating and verifying PCB layout rules
- Performing DDR4 static timing and signal integrity analysis 
- Modeling and analyzing power delivery networks
- Performing physical measurements to collect data for design validation and simulation correlations
- Driving methodology enhancements and automation - improving performance and efficiency 
- Development simulation tools with EDA vendor(s) whenever needed for analysis. 
- Mentor junior engineers and interns 

Who You'll Work With:

Cisco Enterpriese Hardware SI team is seeking a signal integrity Technical Leader for leading the SI team, design and analysis of high speed interfaces and power distribution network. The candidate will participate in the definition and design of current and next generation ASIC, package, printed circuit board (PCB), and system interconnect. The individual will be the key person to work closely with system architects, ASIC engineers, CAD engineers and lead other very talented and knowledgeable SI engineers in creation of next generation high performance networking products. 

Who You Are:

- Self-motivation, Strong teamwork, Strong communication skills and Out of the box thinking with the strong desire to innovate are essential.
- Working experience with high speed NRZ and PAM4 Serdes, PLLs, CDR and FEC
- Hands on experience with ASIC development focused on Serdes, DDR4 and IO IP selection, package design and simulation, ASIC level power integrity
- Solid knowledge of the IEEE 802.3 and OIF specifications for 25Gbps and 56Gbps Serdes Interfaces
- Hands on experience with a broad range PCB materials, understanding cost/performance trade offs 
- Knowledge of DDR4 simulation methodology and timing analysis
- Working knowledge of system level power integrity and budgeting (DC, AC, transient analysis)
- Well versed with 3-D field solvers 
- In depth understanding of electromagnetic theory is required
- Working knowledge of AMI models and tools (SiSoft QCD and ADS)
- Strong lab skills and measurement experience are required (VNA, TDR, Real Time Scope, BERT)
- Strong tools knowledge (HFSS, ADS, SiSoft QCD and QSI, Cadence PowerSI/DC, Allegro, Simbeor, HSpice)
- Generating the routing requirements and electrical margins for specific interfaces and verifying their correctness 
- Ability to define a project schedule and requirements, then deliver to that schedule

Educational Background

PhD/MSEE combined with 7-10 years of related experience, or BSEE combined with 10-15+ yrs related experience.