Lead FPGA design verification on large scale data path hardware acceleration FPGA.
Education and Experience Required:
Bachelor’s or Master’s degree in equivalent experience.
8+ years of ASIC/FPGA Verification experience.
Knowledge and Skills:
You are proficient in ASIC/FPGA verification using UVM/System Verilog.
Experience with EDA tools: VCS,Spyglass,nLint.
You are proficient in verifying complex blocks, clusters and top level
You can build testbench from scratch, hands on experience with System Verilog constraints, structures and classes.
You are familiar with Perl and/or Python scripting
You have the ability to collaborate with cross-functional teams, and possess the drive to learn and grow
Strong domain experience on one or more protocols – PCIe, Ethernet, DMA, DDR.
Structured approach to design and problem-solving
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