Principal Engineer- ASIC Design Verification

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
    Cloud and Data Center, Networking
  • Job Id


The Design Verification PE will technically lead all full-chip verification efforts (simulation, emulation, lab bring-up) from the very early stages of architecture definition and all the way thru the mass production of the chip in targeted Cisco systems. Solid line run a small team of logic design verification engineers focusing on top-level DV and dotted-line manage a larger team of design verification engineers executing top-level DV; Drive DV methodology, verification execution, infrastructure development and lab bring-up. As part of that role you’ll plan, track and facilitate execution of complex ASIC verification efforts including simulation and emulation; you’ll provide technical guidance to verification leads and engineers, ensure timely completion of projects and achieve high quality bug free silicon. 


You’ll report to the chip lead who is fully responsibility for the entire ASIC development effort (design, DV, PD, qualification) and work closely with leads of peer teams including: Architecture, Design, Verification, HW, Diags, SW.


-  You will have a BS or MS degree in either EE or CS and have a minimum of 10 years of relevant management experience in verification of high performance networking ASICs.

-  You will have a consistent track record as a technical lead for complex verification efforts.

-  Good familiarity with all modern ASIC verification methods, including simulation/SystemVerilog/UVM, Emulation

-  Hands-on expertise in one or more of UVM infrastructure development, emulation, lab bring-up

-  Proven track record in planning and budgeting for ASIC verification efforts including all aspects of tools, servers, disks, lab, etc.

-  Must also have a good understanding of all phases of front-end development in ASIC projects, including ASIC architecture, micro-architecture, RTL design, verification, timing closure, physical design and lab validation. Experience in high performance networking silicon is highly desired.

-  You will be a confirmed leader, be able to build and lead teams in a combination of solid and dotted line management. 

-  Consistent track record in planning and budgeting for ASIC verification efforts including all aspects of tools, servers, disks, lab, etc.


-  Ability to scope an ASIC verification program end to end

-  Strong analytical and problem solving skills

-  Ability and willingness to pull-up their sleeves and dive into hands-on work in any aspect of the program that is facing challenges towards a prompt and effective resolution

-  Ability to network, build relationships, and drive effective decision-making across multiple functions and levels within the organization

-  Highly organized, able to prioritize, and juggle multiple work streams to tight deadlines

-  You will have excellent verbal and written communication skills.


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