Physical Design Engineer
Location:Bangalore, Karnataka, India
Area of InterestEngineer - Hardware
Who you'll work with:
Our creative and talented Physical Design team in Bangalore, India. As a member of this team you will be involved in crafting next generation state-of-the-art networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place&route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
What you will do:
- Responsible for RTL2GDS implementation of multi-hierarchy designs in 7nm TSMC technology
- Perform partition, pin assignment and assemble design process tasks
- Participate in defining Physical and Timing Sign-Off conditions
- Work closely with RTL design team to understand the design architecture and drive design physical planning aspects
- As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution
Who you are:
You are a HW engineer with 1-3 years of related work experience with a broad mix of technologies including:
- All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Hierarchical design implementation approach, Timing closure, physical convergence.
- Power Integrity Analysis
- Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7nm technologies.
- Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies
You should also have hands on experience with the following Tool sets
- Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2
- Synthesis Tools: Synopsys DC/DCG
- Formal Verification : Synopsys Formality and Cadence LEC
- Static Timing verification: Primetime-DMSA
- Power Integrity : Apache Redhawk
- Physical Design Verification Synopsys ICV, Mentor Calibre
- Scripting: TCL, Perl is required; Python is a plus
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here's how we do it.
We embrace digital, and help our customers implement change in their digital businesses. Some may think we're "old" (30 years strong!) and only about hardware, but we're also a software company. And a security company. A blockchain company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can't put us in a box!
But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)
Day to day, we focus on the give and take. We give our best, we give our egos a break and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.
So, you have colorful hair? Don't care. Tattoos? Show off your ink. Like polka dots? That's cool. Pop culture geek? Many of us are.
Passion for technology and world changing? Be you, with us!