Hardware Engineer Student - multiple positions

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  • Location:
    Caesarea, Israel
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Intern
  • Technology Interest
    Internet of Everything, Networking
  • Job Id
    1425191
You'll be joining our Cisco Silicon One team which is the center of Cisco’s ASIC design worldwide!

Our engineers deal with all chip design aspects: from definition, architecture, coding to physical design and signoff. 

We are constantly offering several positions in the ASIC development field:


Who You'll Work With

Top industry engineers in a fast-growing Silicon One group @ Cisco worldwide.

You'll be part of our Group driving our game changing next generation network devices - Cisco Silicon One™. Our unique team works in a startup atmosphere inside a stable and leading corporate.

Our design center is very unique - hosting all silicon HW and SW development disciplines inside one site.

We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One™ is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!


Who You Are

  • exceptional B.Sc Electrical Engineer student (graduating in 2025-2026) from leading Israeli Universities with average grades above 85
  • Brilliant ambitious and motivated individual, regardless of previous experience.
  • Team players who enjoy big challenges
  • People who can quickly ramp on multiple, interdisciplinary domains.


Learn more about us right here:

Silicon One Article

Cisco Silicon One movie

Cisco CEO talks to Fortune about 5G Chips

Israeli Calcalist on Leaba Cisco acquisition (in Hebrew)

Cisco Bets Its Business on 'Internet for the Future' Strategy


Why Cisco

We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns. 

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers. 

#WeAreCisco



More information about each option


Design and verification under the front end design team 

Front- End Design team at Cisco Silicon One team. The team is leading the silicon development in Cisco. Our engineers deal with all chip design aspects: definition, architecture, micro architecture, design, verification, sign-off and validation. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.


Physical Design implementation team 

Physical Design team at Cisco Silicon One team. The team is leading the silicon physical implementation in Cisco. Our team deals with all physical design aspects from RTL to GDS: Synthesis, Place & Route, sign-off and physical verification. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.


Signal integrity (SI), Power integrity (PI) and Lab post silicon electrical characterization 

Lab post silicon electrical characterization – very high-speed interfaces characterization and compliance to spec; silicon electrical validation including power, speed, process, and packaging thermal; high usage with lab high speed / RF equipment and automation. 

Signal integrity (SI) and Power integrity (PI): SI of very high-speed interfaces. Layout escape and routes geometries extractions, optimization and sign-off to the spec. Frequency and time domain analysis. PI of very power hungry and analog sensitive supplies, impedance profile extraction, time domain analysis of latest SI/PI tools and flows. Close relations with the IP/Packaging/PCB teams for max optimizations and tradeoffs.

Package design from bump map and spec to full netlist and layout implementation. Large scale, multi die complex structures. Design signoff including high speed routes, LVS, LVL, IR drop etc’. Close relations with the IP/PD/PCB teams for max optimizations of the package design.

We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

If you love the hands on experiences this is the right team for you!

  • Practical engineer – advantage!
  • Experience in lab test/characterization, SI/PI analysis and board/package design is not a must. 


Analog/Mixed Signal Design team 

You will architect and design analog/mixed-signal circuits for a highly advanced high-speed IP on industry leading CMOS process nodes.

The work content encompasses all design stages, from definition to final layout sign-off. 

You will join a small team of top industry analog and system professionals


DFT engineer

As DFT engineer you will be involved in the chip entire life cycle: both pre silicon and post silicon, taking part in bringing our product with high quality to our customers.

It will be a big plus if you have experience in working on the DFT area from the definition via the design and up to full production


Message to applicants applying to work in the U.S. and/or Canada:

When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday, plus a day off for their birthday. Employees accrue up to 20 days of Paid Time Off (PTO) each year and have access to paid time away to deal with critical or emergency issues without tapping into their PTO. We offer additional paid time to volunteer and give back to the community. Employees are also able to purchase company stock through our Employee Stock Purchase Program.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;

1.5% of incentive target for each 1% of attainment between 50% and 75%;

1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

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