DFT Lead Engineer Design-for-Test Hardware Engineer, Silicon Engineering

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    Networking
  • Job Id
    1246048
New
Please note this posting is to advertise potential job opportunities. This exact role may not be open today, but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

Our creative and talented team as Design for Test Hardware Engineer in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the DFT and quality process through the entire Implementation flow. 

"What You'll Do"

  • Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.
  • Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL
  • Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.  
  • Your team will be responsible for Innovative Hardware DFT for new silicon device models, bare die & stacked die- driving re-usable test and debug strategies.  
  • The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.

"Who You Are" 

You are an ASIC Design for Test Hardware Engineer with 5+ years of related work experience with a broad mix of technologies including: 

  • Excellent knowledge of latest state-of-the-art trends in DFT and test.
  • Hands-on experience with Jtag protocols, Scan and BIST architectures, including memory BIST, IO BIST
  • Verification skills include, System Verilog, UVM, Logic Equivalency checking and validating the Test-timing of the design.
  • Experience working with Gate level simulation, and debug with VCS and other simulators.
  • Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 
  • Strong verbal communication skills and ability to thrive in a dynamic environment
  • Scripting skills: Python/Perl.
  •  Bachelor's or a Master’s Degree in Electrical or Computer Engineering required