DFT Engineer :: Design for testability, JTAG, Scan and BIST,ATPG :: 7+ Years
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Location:Bangalore, India
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Alternate LocationAhmedabad, India
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Area of InterestEngineer - Hardware
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Job TypeProfessional
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Technology Interest*None
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Job Id1431529
Who You'll Work With
Be part of the development organization as an ASIC implementation engineer in Bangalore, India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, and backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team, you will be involved in creating groundbreaking next-generation networking chips. You will be led to drive the DFT and quality process through the entire Implementation flow with additional exposure to physical design signoff activities.
What You'll Do
- · Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.
- · Responsible for the development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL
- · Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.
- · Your team will be responsible for Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die-driving re-usable test and debug strategies.
- · The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.
Who You Are
- · You are an ASIC Design DFT Engineer with 7+ years of related work experience with a broad mix of technologies including:
- · Knowledge of the latest state-of-the-art trends in DFT, test and silicon engineering.
- · Hands-on experience with Jtag protocols, Scan and BIST architectures, including memory BIST, IO BIST
- · Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
- · Experience working with Gate level simulation, and debug with VCS and other simulators.
- · Knowledge/working experience on DFT modules integration.
- · Knowledge/working experience on developing the DFT module specific testbench , testcases to verify them.
- · Understanding the testbench in System Verilog/UVM/VMM is addon
- · Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- · Strong verbal communication skills and ability to thrive in a dynamic environment
- · Scripting skills: Python/Perl.
- · Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
We Are Cisco
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all.
We accept digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!
But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)
Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take the difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward.
So, you have colourful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world-changing? Be you, with us!
Who You'll Work With
Be part of the development organization as an ASIC implementation engineer in Bangalore, India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, and backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team, you will be involved in creating groundbreaking next-generation networking chips. You will be led to drive the DFT and quality process through the entire Implementation flow with additional exposure to physical design signoff activities.
What You'll Do
- · Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.
- · Responsible for the development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL
- · Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.
- · Your team will be responsible for Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die-driving re-usable test and debug strategies.
- · The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.
Who You Are
- · You are an ASIC Design DFT Engineer with 7+ years of related work experience with a broad mix of technologies including:
- · Knowledge of the latest state-of-the-art trends in DFT, test and silicon engineering.
- · Hands-on experience with Jtag protocols, Scan and BIST architectures, including memory BIST, IO BIST
- · Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
- · Experience working with Gate level simulation, and debug with VCS and other simulators.
- · Knowledge/working experience on DFT modules integration.
- · Knowledge/working experience on developing the DFT module specific testbench , testcases to verify them.
- · Understanding the testbench in System Verilog/UVM/VMM is addon
- · Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- · Strong verbal communication skills and ability to thrive in a dynamic environment
- · Scripting skills: Python/Perl.
- · Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
We Are Cisco
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all.
We accept digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (36 years strong) and only about hardware, but we’re also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!
But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)
Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take the difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward.
So, you have colourful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world-changing? Be you, with us!
When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.
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Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco’s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco’s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community.
Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows:
.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
1.5% of incentive target for each 1% of attainment between 50% and 75%;
1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.
For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.
