Asic Design Engineer

  • Location:
    San Jose, California, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
  • Job Id

What You'll Do

We are looking for an experienced and talented Asic Design Engineer. You will have an ASIC design background with hands-on experience in design, verification, physical design, system testing, with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.


  • Architectural work: in-depth understanding of the architecture, and identification of problems and solutions.  
  • All aspects of implementation: specification, design, verification, timing-closure, power-optimization, and flow automation.
  • Physical design work: timing path analysis, optimization of the logic for low power and area; highlighting issues and best practices for power and area optimization.
  • Create documentation and improve best practices to make product successful.
  • Coordinating with other engineers in project milestones: schedule, power, area. 

Who You Are

  • Worked in architecture and definition of high-scale, high-performance ASICs. 
  • Proven experience in implementation: specification, design, verification, formal verification, system testing.
  • Proven experience in physical design aspects (Front End): timing analysis and closure, power/area optimizations, macro size/placement analysis. 
  • Proven experience in high bandwidth memory subsystems and timing closure.
  • Proven experience in flow automation (scripting, Makefile, etc), and establishing guidelines for the team. 
  • Good communication skills, and proven leadership to accurately describe issues/improvements and lead team for on-time completion. 
  • 6+ years of hands on experience in large-scale, high-performance ASICs.
  • BS/MS in EE/CS.

Minimum Qualifications

  • Understanding of networking
  • End-to-end design experience from Verilog to gates, block planning, area/timing closure is strongly desired.
  • RTL development and verification (VCS, System Verilog, UVM, Formal verification)
  • Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS.
  • Gate-level understanding of RTL and Synthesis
  • Programming/scripting skills (C, C++, Perl)

Who You'll Work With

Come join us and take part in shaping Cisco’s revolutionary Service Provider and Enterprise solutions by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!

Why Cisco

We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren't afraid to change the way the world works, lives, plays and learns.

We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.

#We Are Cisco.