Analog Mixed-Signal Layout Design Engineer
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Location:Offsite, Carlsbad, California, US
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Area of InterestEngineer - Hardware
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Compensation Range146000 USD - 205400 USD
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Job TypeProfessional
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Technology InterestCloud and Data Center
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Job Id1439354
The application window is expected to close on: 05/09/2025.
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.
Meet the Team
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design optical modules for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world.
You will be part of our Analog Mixed-Signal Layout Design team and collaborate with the Analog Mixed-Signal Circuit Design teams and Silicon Photonics design teams to create high-speed, high-performance, and highly integrated optical transceivers.
Your Impact
In this role, you will play a crucial part in producing high-quality physical designs for high-speed connectivity in hyperscale data centers and other critical networks. You will support Circuit Designers by contributing to the CAD layout of physical designs for high-performance analog/mixed-signal optical transceiver circuits, utilizing advanced process technologies. Your work will involve designing components like frequency synthesizers, clock distribution systems, transmitters, and more.
• Create detailed analog and mixed-signal IC layout designs for analog, covering stages from floor planning, block design, and top-level design to tapeout
• Collaborate closely with circuit design engineers to ensure layouts meet the required specifications for electrical, performance, matching, and reliability
• Perform verification on advanced node technologies, ensuring compliance with DRC, LVS, antenna rules, density rules, ERC, Virtuoso XL compliance, reliability, and in-house best practices.
• Optimize layouts to minimize noise coupling, crosstalk, electromigration, matching issues, latch-up prevention, and ensure ESD robustness.
• Perform parasitic extraction to ensure that layout achieves targeted performance, considering parasitic effects.
• Use industry-standard CAD layout tools such as Cadence Virtuoso, Cadence Pegasus, and Siemens Calibre, among others.
• Support tape-out activities, including chip-level integration, full-chip verification, and documentation.
• Contribute to methodology enhancements, automation, and layout efficiency improvements to streamline the design process.
• Coordinate with the photonics team and other cross functional teams to improve the overall system.
• Divide layout tasks into component parts to work in parallel with other layout design engineers when it helps accelerate project timelines.
• Provide ongoing schedule guidance on tasks to the manager.
• Complete checklists and follow company design flows and other quality assurance methodologies.
• Present your work in layout reviews, review layouts from other layout design engineers, and collect feedback for continuous improvement of circuit layouts and documentation.
• Perform post-layout analysis and debugging to support silicon validation and characterization activities when necessary.
Minimum Qualifications:
• Bachelor's degree or equivalent experience in related field
• 8+ years experience of mask design experience in sub-micron CMOS (7nm or smaller geometries)
• 3+ years of experience in high precision analog/mixed signal circuit
• Experience with layout in the Cadence Virtuoso design environment and Siemens Mentor Calibre or Cadence Pegusus verification tool
Preferred Qualifications:
• Bachelor of Science degree in Electrical Engineering (BSEE) is preferred
• 10+ years of proven experience in analog mixed-signal layout design, particularly in high-speed circuits (more than 10 GHz)
• Working knowledge of debugging with DRC/LVS/ERC with Cadence Pegasus or Siemens Calibre
• Experience translating concepts such as parasitics, matching, crosstalk, transistor layout dependent effects, latchup, IR drop, electromigration and triple well processes into physical design constraints
• Proficient experience in chip-level floor planning, analog block integration and the ability to use productivity-enhancing tools and design scripts is desirable
#WeAreCisco
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Our passion is connection—we celebrate our employees’ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.
We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer—80 hours each year—allows us to give back to causes we are passionate about, and nearly 86% do!
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When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.
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.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
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