ASIC development Hardware Engineer Intern – multiple positions
Alternate LocationTel-Aviv, Israel
Area of InterestEngineer - Hardware
Location: Caesarea or Tel-Aviv, Israel
Start Date: Flexible - in accordance with the university schedule
You'll be joining our Cisco Silicon One team which is the center of Cisco’s ASIC design worldwide!
Our engineers deal with all chip design aspects: from definition, architecture, coding to physical design and signoff.
We are constantly offering several positions in the ASIC development field:
- Design and verification under the front-end design team
- Physical Design implementation team
- Signal integrity (SI), Power integrity (PI) and Lab post silicon electrical characterization
- Analog/Mixed Signal Design team
- DFT (Design for testing) design team
Who You'll Work With
Top industry engineers in a fast-growing Silicon One group @ Cisco worldwide.
You'll be part of our Group driving our game changing next generation network devices - Cisco Silicon One™. Our unique team works in a startup atmosphere inside a stable and leading corporate.
Our design center is very unique - hosting all silicon HW and SW development disciplines inside one site.
We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all Cisco's future routing products.
Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.
Cisco Silicon One™ is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!
Who You Are
- exceptional B.Sc Electrical Engineer student (graduating in 2022-2023) from a TAU, Technion, Ben-Gurion or Hebrew University with average grades above 85
- Brilliant ambitious and motivated individual, regardless of previous experience.
- Team players who enjoy big challenges
- People who can quickly ramp on multiple, interdisciplinary domains.
Learn more about us right here:
We connect everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. And we do it in style with unique personalities who aren’t afraid to change the way the world works, lives, plays and learns.
We are thought leaders, tech geeks, pop culture aficionados, and we even have a few purple haired rock stars. We celebrate the creativity and diversity that fuels our innovation. We are dreamers and we are doers.
More information about each option
Front- End Design team at Cisco Silicon One team. The team is leading the silicon development in Cisco. Our engineers deal with all chip design aspects: definition, architecture, micro architecture, design, verification, sign-off and validation. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
Physical Design team at Cisco Silicon One team. The team is leading the silicon physical implementation in Cisco. Our team deals with all physical design aspects from RTL to GDS: Synthesis, Place & Route, sign-off and physical verification. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
Lab post silicon electrical characterization – very high-speed interfaces characterization and compliance to spec; silicon electrical validation including power, speed, process, and packaging thermal; high usage with lab high speed / RF equipment and automation.
Signal integrity (SI) and Power integrity (PI): SI of very high-speed interfaces. Layout escape and routes geometries extractions, optimization and sign-off to the spec. Frequency and time domain analysis. PI of very power hungry and analog sensitive supplies, impedance profile extraction, time domain analysis of latest SI/PI tools and flows. Close relations with the IP/Packaging/PCB teams for max optimizations and tradeoffs.
Package design from bump map and spec to full netlist and layout implementation. Large scale, multi die complex structures. Design signoff including high speed routes, LVS, LVL, IR drop etc’. Close relations with the IP/PD/PCB teams for max optimizations of the package design.
We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
If you love the hands on experiences this is the right team for you!
- Practical engineer – advantage!
- Experience in lab test/characterization, SI/PI analysis and board/package design is not a must.
You will architect and design analog/mixed-signal circuits for a highly advanced high-speed IP on industry leading CMOS process nodes.
The work content encompasses all design stages, from definition to final layout sign-off.
You will join a small team of top industry analog and system professionals
As DFT engineer you will be involved in the chip entire life cycle: both pre silicon and post silicon, taking part in bringing our product with high quality to our customers.
It will be a big plus if you have experience in working on the DFT area from the definition via the design and up to full production
The health and safety of Cisco's employees, customers, and partners is a top priority. Our goal is to protect and mitigate the spread of COVID-19 infection for strong business resiliency during the pandemic. Therefore, Cisco may require new hires to be fully vaccinated against COVID-19 if the role requires business-related travel, meeting with customers/partners (including visiting third-party sites on behalf of Cisco), attending trade events, and Cisco office entry, unless otherwise prohibited by applicable law, and in countries where COVID-19 vaccination is legally required. The company will consider legally required accommodations/exceptions for medical, religious, and other reasons as per the requirements of the role and in accordance with applicable law. Additional information will be provided to candidates about the requirements and accommodation process at the offer time based on region.