ASIC Physical Design Timing Engineer Technical Leader - Acacia

  • Location:
    Maynard, Massachusetts, US
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    Cloud and Data Center
  • Job Id
    1329235

This position is a primary member of a team responsible for executing project deliverables and processes necessary to successfully specify, develop, and release to production highly integrated ASICs.

Key Essential Functions

·       Deliver on power delivery methodology and flow.  Involve major stakeholders across analog and digital teams to drive power analysis, electromigration and IR signoff process corner decisions.

·       Research and drive latest timing technologies into Acacia, like electromigration statistical budgeting techniques.  Work with RTL designers for appropriate vector analysis.  Run signoff power grid analysis at the top level, drive closure of issues across the team.  Interface with EDA vendors on issues/features/enhancements on tools.

·       Deliver on physical design implementation activities such as floorplanning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, power grid analysis, physical verification DRC/LVS across all major EDA tool suites.

·       Work closely with RTL designers to debug and root-cause Physical Implementation issues related to design and tools etc. and arrive at a feasible solution through the augmentation of input and design collateral.

Other Duties

  • Perform other duties as assigned.

Minimum Qualifications, Experience, Skills, Education and Certifications

·       Bachelor’s Degree (or higher) in electronic engineering, or the equivalent qualification in training and experience

·       At least 12 years of professional engineering experience, including experience in advanced technology nodes:  28nm, 16nm and below

·       Familiar with industry standard Timing methodologies and tools from Cadence, Synopsys and/or Mentor

·       Good scripting skills with Perl and TCL

·       Successful execution of ASICs from product definition to production release

·       Solid analytical, communication and presentation skills

·       Self-motivated and the ability to drive without supervision

Other Considerations/Qualifications

·       Finfet expertise

·       Prior experience in telecom design space

·       Experience with digital signal processing algorithms is a plus

·       Exceptional written & verbal communication skills

Special Physical/Travel Requirements

·       None

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or veteran status.


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