ASIC Physical Design Engineer
Location:San Jose, California, US
Area of InterestEngineer - Hardware
Compensation Range144800 USD - 214100 USD
WHO YOU'LL WORK WITH:
Our creative and talented team as Physical Design Engineer in San Jose, CA. You will work with ASIC Front-end teams to understand chip architecture and drive physical aspects early in the design cycle, driving them to refine their design for physical design closure. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the backend process through the entire Implementation flow including floor planning, Placement, CDC checks, static timing verification and equivalence checks, with special focus on power and die size optimization.
WHAT YOU WILL DO:
- Responsible for floor planning of full chip and key sub chips, handing off your floorplans and physical synthesis results to physical implementation.
- Responsible for driving timing closure through physical synthesis and P&R tools and working with ASIC vendors.
- As member of physical/implementation design team, drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress.
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution.
WHO YOU ARE:
You are a HW engineer with 7+ years of related work experience with a broad mix of technologies including:
- All aspects of ASIC integration including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
- Hierarchical design approach, top-down design, budgeting, timing and physical convergence.
- Experience on integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain
- Experience with large designs (>100M gates) utilizing state of the art sub 7/5 nm technologies.
- Familiarity with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and power/ thermal management, power islands.
You should also have hands on experience with the following Tool sets
- Floor planning and P&R tools: Cadence Innovus
& Synopsys ICC2),
- Synthesis Tools: Synopsys DC/DCG
- Formal Verification : Synopsys Formality and Cadence LEC
- Static Timing verification (Primetime/PTPX).
- Familiarity with Physical Design Verification Flows is a plus.
- Scripting: TCL, Perl is required; Python is a plus
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
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When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.
U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday, plus a day off for their birthday. Employees accrue up to 20 days of Paid Time Off (PTO) each year and have access to paid time away to deal with critical or emergency issues without tapping into their PTO. We offer additional paid time to volunteer and give back to the community. Employees are also able to purchase company stock through our Employee Stock Purchase Program.
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