ASIC Engineering Technical Leader

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  • Location:
    Bangalore, India
  • Alternate Location
    Ahmedabad, India
  • Area of Interest
    Engineer - Hardware
  • Job Type
    Professional
  • Technology Interest
    *None
  • Job Id
    1431539

Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.

What you will do:

  • Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology.
  • Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
  • Good understanding of different CTS strategies and providing the feedback to Implementation Team.
  • As member of physical design team, drive methodologies and “best known methods” to streamline and automate physical design work.
  • STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
  • Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
  • Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions.
  • Evaluate multiple timing methodologies/tools on different designs and technology nodes.
  • Good scripting skills (TCL/SHELL/PERL/Python) is a MUST

Who you are:

You are an ASIC engineer with 15+ years of related work experience with a broad mix of technologies including:

  • All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  • Hierarchical design implementation approach, Timing closure, physical convergence.
  • Power Integrity Analysis
  • Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
  • Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies.

You should also have hands on experience with the following Tool sets

  • Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2
  • Synthesis Tools: Synopsys DC/FC
  • Formal Verification : Synopsys Formality and Cadence LEC
  • Static Timing verification: Primetime-DMSA
  • Power Integrity : Apache Redhawk
  • Physical Design Verification Synopsys ICV, Mentor Calibre
  • Scripting: TCL, Perl is required; Python is a plus

Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experienceWe are looking for high achievers who love challenging environment to join our team.

We Are Cisco

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it.

We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)

Day to day, we focus on the give and take. We give our best, we give our egos a break, and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.

So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool.

     
Message to applicants applying to work in the U.S. and/or Canada:

When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday, plus a day off for their birthday. Employees accrue up to 20 days of Paid Time Off (PTO) each year and have access to paid time away to deal with critical or emergency issues without tapping into their PTO. We offer additional paid time to volunteer and give back to the community. Employees are also able to purchase company stock through our Employee Stock Purchase Program.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows:

.75% of incentive target for each 1% of revenue attainment up to 50% of quota;

1.5% of incentive target for each 1% of attainment between 50% and 75%;

1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

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