Location:San Jose, California, US
Area of InterestEngineer - Hardware
Technology InterestBig Data, Analytics, Cloud and Data Center, Networking
What You'll Do
The Datacenter Networking Business Unit is looking for an expert Verification Engineer to engage in new development of our Nexus 9K family. You will have an ASIC verification background with hands-on experience in RTL and verification, in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume semiconductor markets.
Who You'll Work With
Data Center is one of Cisco’s recent acquisitions and fastest growing teams. This team, within the Datacenter business unit, developed the Nexus 9000 line of data center switches and Application Centric Infrastructure, Cisco’s premier datacenter SDN solution. Our team, within Datacenter Networking, is responsible for driving integration of the Nexus 9000 and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.
Who You Are
You will collaborate closely with the architecture, hardware, and software teams to design, develop, verify, and validate Data Center networking ASICs working across product generations, networking technologies, and protocols. There are only a handful of teams in the world that implement and deliver successful ASICs at this performance and scale, and we take pride in the impact of our work. Every time you access the internet, chances are, your data is going through one of our ASICs.
- Participate in the development of high-performance ASICs from specification to tape-out, including RTL, synthesis, physical design, and timing closure
- Maintain and enhance existing designs using Verilog/SystemVerilog
- Participate in the Implementation of new designs using Verilog/SystemVerilog
- Triage and troubleshoot failures down to the root cause
- Actively work with the verification team to deliver ASICs with high quality
- Actively work with the physical design team to resolve implementation and timing issues
- Develop tests and debug ASICs in the emulation
- Perform diagnostics and tests for ASICs in the lab
Education and Experience Required:
- Bachelor’s or Master’s degree in Electrical Engineering
- 0-2 years of ASIC design and verification experience
Knowledge and Skills:
- Excellent Verilog and SystemVerilog programming and debugging skills
- Scripting experience (Python, Perl, TCL, shell programming)
- Proficient in synthesis constraints
- Proficient in physical design and implementation
- Ability to write and debug test
- Ability to debug system-wide issues
- Good written and verbal communication skills
- Collaborative and team-focused with the drive to learn and grow
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