ASIC Design for Test Technical Leader
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Location:San Jose, California, US
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Area of InterestEngineer - Hardware
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Compensation Range184000 USD - 266000 USD
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Job TypeProfessional
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Technology InterestNetworking
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Job Id1424968
The application window is expected to close on 12/15/2024
This is an onsite role and will require working out of the Milpitas/San Jose office location.
Who We Are
The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.
Who You'll Work With
You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.
What You'll Do
- Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
Minimum Qualifications:
- Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 10 years of experience.
- Knowledge of the latest innovative trends in DFT, test and silicon engineering.
- Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design
- Knowledge of the latest innovative trends in DFT, test and silicon engineering. • Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
- Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
- Prior experience working with Gate level simulation, debugging with VCS and other simulators.
- Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Prior experience with Scripting skills: Tcl, Python/Perl.
Preferred Qualifications:
- Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
- DFT CAD development – Test Architecture, Methodology and Infrastructure
- Background in Test Static Timing Analysis
- Past experience with Post silicon validation using DFT patterns.
Why Cisco?
#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re "old" (36 years strong) and only about hardware, but we’re also a software company. And a security company.
We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you can’t put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it).
Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart.
Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us!
When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.
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.75% of incentive target for each 1% of revenue attainment up to 50% of quota;
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