ASIC Design Verification
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Location:San Jose, California, US
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Alternate LocationAustin, Texas
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Area of InterestEngineer - Hardware
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Compensation Range107000 USD - 186800 USD
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Job TypeProfessional
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Technology InterestNetworking
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Job Id1432973
The application window is expected to close on 1/10/2025
This role can sit in our Milpitas/San Jose office location, or remotely in Austin, TX.
What You'll Do:
It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. Cisco Common ASIC Group is looking for a Senior ASIC Verification Engineer to drive existing projects and engage in new development of our next-generation switching systems.
As part of the ASIC team, you will be developing the ASICs at the heart of each of these switch products. There are only a very few teams worldwide that implement such devices. Every time you access the Internet, chances are, your data's been through one of our switches.
Who You'll Work With:
You will work with Cisco’s best-in-class switching solution team. Our team is responsible for driving integration of the Nexus systems and ACI with software, including OpenStack, Docker, and Open vSwitch, to help our customers build multitenant clouds.
Who You Are:
You are a talented, motivated ASIC verification engineer to join the team and contribute to the verification of very complex ASICs. You will have a Design Verification background, and hands-on experience in System Verilog and UVM methodology, with in-depth knowledge of C++, scripting, as well as ASIC design and verification flow.
You’ll be part of the Cisco Common ASIC Group, focusing on developing and upgrading various test benches and contributing to different aspects of verification infrastructure.
You will collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation, and during ASIC bring-up.
Responsibilities Include:
- Create block level test benches including components like drivers/monitors/sequences
- Maintaining existing test benches for block level and/or cluster level
- Upgrading test benches to accommodate new features
- End-to-end verification of various design blocks
- Developing test plans, cover points
- Upgrading/updating configuration/reset sequences (APIs)
- Collaboration with designers/verification engineers to perform cross-block verification
- Writing tests, and debugging regressions
- Contributing to top level verification
- Be a part of emulation testing efforts
Education and Experience Required:
- Master’s degree in EE (Electrical & Electronics) or CE (Computer Engineering) with 2+ YoE in Design Verification
- Bachelor’s degree in EE or CE and 3+ YoE in Design Verification
Knowledge and Skills:
- Required Skills:
- Hands-on and deep understanding of System Verilog and UVM methodology
- Ability to write System Verilog constraints, construct testbench including scoreboard, agents, sequencers, and monitors
- Ability to debug issues independently
- Proficient in functional coverage and constrained random DV environments
- Good written and verbal communication skills
- Collaborative and team-focused, with the drive to learn and grow
- Nice to have Skills:
- Basic scripting experience (Python, Perl, shell programming)
- Nice to have C, C++ programming and debugging skills
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When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidate's hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process.
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