ASIC Design Verification Engineer
Location:San Jose, California, US
Area of InterestEngineer - Hardware
Technology InterestCloud and Data Center, Networking
As part of Cisco Silicon one portfolio, we are looking to have highly motivated and skilled Asic engineer to be part of our team to solve complex problems and develop solutions for our family of routing products.
- Participate in architecture definition and modeling.
- Write micro-architecture specification and reviews.
- Code Synthesisable RTL in Verilog/System Verilog
- Run/debug simulations using VCS (or simulator)
- Synthesize RTL code using design compiler and constraints
- Understand and run Static timing analysis
Qualifications and Skills:
- Bachelors or Masters in Electrical/Computer engineering.
- 4+ years of experience in high performance ASIC's and have gone through at least two design tapeouts
- Good understanding of ASIC design and verification methodologies and flow
- Hands-on experience with Verilog/System Verilog and simulators/synthesis/static timing analysis tools
- Knowledge of scripting language : Perl/Python
- Good problem solving skills.
- Good communication and team skills.
- Networking knowledge preferred, but not essential.
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