ASIC Design Verification Engineer
Location:San Jose, California, US
Area of InterestEngineer - Hardware
Technology InterestCloud and Data Center, Networking
At Cisco we develop the technology that forms the backbone of the internet. We develop solutions that address challenges and prepare the foundation for the internet of the future. Our Hardware and Software solutions are tightly coupled with the development cycles that gives us an unparalleled advantage in enabling our customers adopt the latest what technology can offer. As part of Cisco Silicon One (#CiscoSiliconOne) our team develops complex, high-performance, feature-rich ASICs used in Cisco's networking products and third-party custom-built hardware systems. We invite highly motivated and skilled engineers to be part of our team to solve complex problems and develop solutions befitting our mission to connect the unconnected.
* Participate in architecture definition and modeling.
* Contribute in micro-architecture specification and reviews.
* Partake in verification environment architecture and methodology.
* Carry out testplanning and execution of testplan.
* Collaborate with design team members to effectively test, verify, and debug DUT for successful tapeout.
* Engage in post-silicon bringup and debug in the lab.
* Mentor and enable other engineers.
* Lead and oversee design verification efforts of a cluster of blocks.
Qualifications and Skills:
* Bachelors or Masters (preferred) in Electrical/Computer engineering.
* Experience (atleast 5+ years) in high-performance ASIC verification.
* Good understanding of ASIC design and verification methodologies and flows.
* Hands-on experience with HVL and HDL languages and tools, scripting and programming languages (verilog, SV, C++, Perl and/or Python etc…).
* Proficient in object oriented programming.
* Good understanding of constraint random stimulus generation methodology.
* UVM experience is required
* Good problem solving skills.
* Good communication and team skills.
* Networking knowledge preferred, but not essential.