ASIC DFT Engineer

  • Location:
    Bangalore, India
  • Area of Interest
    Engineer - Hardware
  • Job Type
  • Technology Interest
    Cloud and Data Center, Networking, Service Provider
  • Job Id

Who you'll work with:

Be part of the development organization as an ASIC implementation engineer in Bangalore, India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive design for test requirements early in the design cycle. As a member of this team you will be involved in creating cutting edge next generation networking chips. You will be the lead to drive the DFT and quality process through the entire Implementation flow with additional exposure to physical design signoff activities.

What You'll Do:

  • Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the design.
  • Responsible for development of innovative DFT IP in collaboration with the cross-functional teams, and play a key role in full chip design integration with the testability features integrated in the RTL
  • Work closely with the design/design-verification and physical design teams to enable the integration and validation of the Test logic in all phases of the design, and back-end implementation flow.
  • Your team will be responsible for Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die- driving re-usable test and debug strategies.
  • The job requires the candidate to have good scripting skills and the ability to design and debug with minimal oversight.

Who You Are:

You are an ASIC Design for Test Hardware Engineer with 7+ years of related work experience with a broad mix of technologies including:

  • Knowledge of latest state-of-the-art trends in DFT, test and silicon engineering.
  • Hands-on experience with Jtag protocols, Scan and BIST architectures, including memory BIST, IO BIST
  • Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design.
  • Experience working with Gate level simulation, and debug with VCS and other simulators.
  • Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
  • Strong verbal communication skills and ability to thrive in a dynamic environment
  • Scripting skills: Python/Perl.
  • Bachelor's or a Master’s Degree in Electrical or Computer Engineering required

We Are Cisco

#WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference. Here’s how we do it.

We embrace digital, and help our customers implement change in their digital businesses. Some may think we’re “old” (30 years strong!) and only about hardware, but we’re also a software company. And a security company. An AI/Machine Learning company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do – you can’t put us in a box!

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)

Day to day, we focus on the give and take. We give our best, we give our egos a break and we give of ourselves (because giving back is built into our DNA.) We take accountability, we take bold steps, and we take difference to heart. Because without diversity of thought and a commitment to equality for all, there is no moving forward.

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