ASIC DFT (Design For Test) Engineer (10 - 15 Years, Leadership experience needed)
Location:Bangalore, Karnataka, India
Area of InterestEngineer - Hardware
Technology InterestInternet of Everything, Networking, Software Development, Testing
What You'll Do
As a member of Cisco’s Central DFT team, you’ll be responsible for architecting, implementing and verifying the ASIC Design-for-Test (DFT) features that support silicon screening, in-system test, debug and diagnostics. You are a hands-on technical lead who will drive DFT insertion of Scan/ATPG, MemoryBist, Jtag protocols and new innovative DFT IP. You will work closely with the ASIC design teams to enable the integration and validation of Test logic in all phases of the design and back-end implementation flows. You will be accountable for DFT feature sign-off for silicon tape-out and post-silicon validation. You will work with Hardware Platform, Diagnostic and ATE Test teams to validate all DFT silicon features and test patterns. Support silicon life-cycle quality as needed.
Who You'll Work With
You will influence and collaborate with many groups within Cisco including ASIC development, System Platform, Software Diagnostics, ATE Test and Silicon Operations. As a member of this team you will be involved in building groundbreaking next generation networking chips and driving DFT quality throughout the entire Implementation flow.
Who You Are
You are an ASIC Design for Test(DFT) lead engineer with 9+ years of experience including:
Excellent knowledge of the latest state-of-the-art elements in DFT and Test. Hands-on design experience in DFT insertion and verification of Scan/ATPG, MemoryBist and Jtag protocols using commercial test generation tools for large complex designs. Tool set includes : VCS, Design Compiler, Spyglass, TetraMax, SMS, BSD Compiler. Cross-Clock Domain Crossing, Primetime.
Previous experience leading a team and driving technical execution results. Experience with DFT silicon sign-off for tape out.
Verification skills include Verilog, UVM, Logic Equivalency checking and validating the test-timing of the design. Experience working with Gate level simulation and debug with VCS and other simulators.
Post-silicon validation and debug experience including feature validation, characterization and yield analysis.
Strong verbal communication skills and ability to thrive in a dynamic environment.
Bachelor's or a Master’s Degree in Electrical or Computer Engineering required
The Internet of Everything is a phenomenon driving new opportunities for Cisco and it's transforming our customers' businesses worldwide. We are pioneers and have been since the early days of connectivity. Today, we are building teams that are expanding our technology solutions in the mobile, cloud, security, IT, and big data spaces, including software and consulting services. As Cisco delivers the network that powers the Internet, we are connecting the unconnected. Imagine creating unprecedented disruption. Your revolutionary ideas will impact everything from retail, healthcare, and entertainment, to public and private sectors, and far beyond. Collaborate with like-minded innovators in a fun and flexible culture that has earned Cisco global recognition as a Great Place To Work. With roughly 10 billion connected things in the world now and over 50 billion estimated in the future, your career has exponential possibilities at Cisco.
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